Intel Unpacks Architectural Innovations and Reveals New Transistor Technology at Architecture Day 2020. Intel Unveils Willow Cove, Tiger Lake and Xe Architectures, Introduces New Transistor Technology as Intel Advances its Six Pillars of Innovation.
At Architecture Day 2020, Intel Chief Architect Raja Koduri, Intel fellows and architects provided details on the progress Intel is making on its six pillars of technology innovation: process and packaging, architecture, memory, interconnects, security and software. Intel is taking full advantage of its unique position to deliver a mix of scalar, vector, matrix and spatial architectures deployed in CPUs, GPUs, accelerators and FPGAs – unified by oneAPI, an industry-standard open programming model to simplify application development.
Intel revealed its 10nm SuperFin technology, representing the largest single intranode enhancement in the company’s history and delivering performance improvement comparable to a full-node transition. Intel also unveiled architectural details of its Willow Cove microarchitecture and the Tiger Lake system-on-chip architecture for mobile client and provided first looks at its fully scalable Xe graphics architectures. Together with Intel’s disaggregated design approach and coupled with advanced packaging technology, XPU offerings and software-centric strategy, the company is focused on developing leading products across its portfolio to customers.
Willow Cove and Tiger Lake CPU Architectures
Willow Cove is Intel’s next-generation CPU microarchitecture. Built on the latest process advancements, 10nm SuperFin technology and the foundation of the Sunny Cove architecture, Willow Cove delivers more than a generational increase in CPU performance with large frequency improvements and increased power efficiency. It also introduces a redesigned caching architecture to a larger non-inclusive 1.25MB MLC and security enhancements with Intel® Control Flow Enforcement Technology.
Tiger Lake will offer intelligent performance and groundbreaking advancements in the key vectors of compute. With optimizations spanning the CPU, AI accelerators and being the first system-onchip architecture with the new Xe-LP graphics microarchitecture, Tiger Lake will deliver more than a generational increase in CPU performance, massive AI performance improvements and a huge leap
in graphics performance with a full set of best-in-class IPs throughout the SoC like the new,
integrated Thunderbolt 4. Tiger Lake SoC architecture offers:
- New Willow Cove CPU core with significant frequency uplift leveraging 10nm SuperFin technology advancements.
- New Xe graphics with up to 96 execution units (EUs) with significant performance-per-watt efficiency improvements.
- Power management – autonomous dynamic voltage frequency scaling in coherent fabric, increased fully integrated voltage regulator efficiency.
- Fabrics and memory – 2x increase in coherent fabric bandwidth, ~86GB/s memory bandwidth, validated LP4x-4267, DDR4-3200; LP5-5400 architecture capability.
- Gaussian Network Accelerator (GNA) 2.0 dedicated IP for low-power neural inferencing offloading from the CPU. ~20% lower CPU utilization on GNA vs. CPU (running noise suppression workload).
- IO – Integrated TB4/USB4, integrated PCIe Gen 4 on CPU for low-latency, high-bandwidth device access to memory.
- Display – up to 64GB/s of isochronous bandwidth to memory for multiple high-resolution displays. Dedicated fabric path to memory to maintain quality of service.
- IPU6 – up to six sensors with 4K30 video, 27MP image, up to 4K90 and 42MP image architectural capability.
Alder Lake – Hybrid Architecture
Intel is advancing its hybrid architecture with Alder Lake, the company’s next-generation client product. Alder Lake will combine two upcoming architectures: Golden Cove and Gracemont, optimized to offer great performance per watt.
Xe Graphics Architectures
Intel detailed the Xe-LP (low power) microarchitecture and software optimized to deliver efficient performance for mobile platforms. Xe-LP is Intel’s most efficient architecture for PC and mobile computing platforms with up to 96 EUs, and comes with new architecture designs including asynchronous compute, view instancing, sampler feedback, updated media engine with AV1 and updated display engine. This will enable new end-user features with instant game tuning, capture, and stream-and-image sharpening. On software optimization, Xe-LP will have driver improvements with a new DX11 path and optimized compiler.
The first Xe-HP chip has been powered on and back from the labs. Xe-HP is the industry’s first multi-tiled, highly scalable, high performance architecture, providing data center-class, rack-level media performance, GPU scalability and AI optimization. It covers a dynamic range of compute from one tile, to two and four tiles, functioning like a multicore GPU. At Architecture Day, Intel demonstrated Xe-HP transcoding 10 full streams of high-quality 4K video at 60 frames per second on a single tile. Another demo showed the compute scalability of Xe-HP across multiple tiles. Intel is now sampling Xe-HP with key customers and plans to enable it in Intel® DevCloud for developers. Xe-HP will be available next year.